As a conventional typical data driver that drives a data line in a liquid crystal display device, a configuration as shown in FIG. 22 is employed. Referring to FIG. 22, this data driver includes a shift register 209, a data register 208, a data latch 207, a level shifter 206, a gray scale voltage generation circuit 205, decoders 203, and an output circuit 202 (amplifiers 201).
An operation of the data driver shown in FIG. 22 will be described. The shift register 209 outputs a shift pulse responsive to a clock signal CLK. The data register 208 sequentially shifts up input video data DATA_IN responsive to the shift pulse from the shift register 209, and distributes the video data according to the number of outputs. The data latch 207 temporarily holds the video data distributed by the data register 208 and outputs all the outputs to the level shifter 206 in unison responsive to a timing of a control signal STB.
A signal output from the level shifter 206 is a digital video signal. This digital signal is converted to an analog gray scale voltage from the digital video signal by circuits from a decoder 203 to the output circuit 202. The gray scale voltage generation circuit 205 is constituted from a resistance string connected between a power supply VA and a power supply VB. From respective terminals (taps) of the resistance string, gray scale voltages corresponding to the number of gray scales are output to the decoders 203 (gray scale voltage selection circuits). Through input of each gray scale voltage and the digital video signal, the decoder 203 selects the gray scale voltage corresponding to the digital video signal, for output to the output circuit 202. The output circuit 202 amplifies the gray scale voltage, for output to each of output terminals 210. Each of the output terminals 210 is connected to one end of a data line for supplying the gray scale voltage to a pixel in the display device.
The decoders 203 and the amplifiers 201 each for outputting the gray scale voltage corresponding to the digital video signal are provided for each of the number of the outputs. Further, the respective gray scale voltages output from the gray scale voltage generation circuit 205 are shared by all of the outputs through gray scale voltage lines.
That is, the decoders 203, gray scale voltage generation circuit 205, and output circuit 202 constitute a digital-to-analog conversion circuit block.
Generally, each data line in the liquid display device is a heavy capacitive load. Thus, as the amplifier in the output circuit 202, an OP amplifier (operational amplifier, referred to as an “op-amp”) is employed. The op-amp as shown in FIG. 15, for example, includes a differential stage circuit 901 and an output stage amplifier circuit 903. The differential circuit (differential stage circuit) 901 includes a differential pair constituted from NMOS transistors M3 and M4 with sources thereof connected in common, a current mirror circuit constituted from PMOS transistors M1 and M2, and an NMOS transistor M9 that serves as a constant current source when a constant bias voltage is applied to a gate terminal thereof. In an example in FIG. 15, the amplifier circuit of an active load type with a source thereof grounded is constructed in the output stage amplifier circuit 903, which includes a PMOS transistor M7 for receiving an output signal from an output point PA of the differential stage circuit and for amplifying the signal and an MOS transistor M10 that serves as a constant current source.
A negative feedback is formed by connection between a node PB and an input to a gate of the transistor M3. Accordingly, a voltage at an output terminal (voltage at an output point PB) is stabilized at a potential at which a drain current of the PMOS transistor M7 of the output stage amplifier circuit that flows in response to a differential amplification output signal and a drain current of the transistor M10 as the constant current source is balanced.
However, in the op-amp, there is a problem that an output offset is generated mainly due to characteristic variations in active devices. As a cause of these characteristic variations, variations in oxide films of the MOS transistors, variations in impurity concentrations of the MOS transistors, variations in device sizes (W/L, where W indicates a channel width and L indicates a channel length), or the like are present. These fabrication variations are determined according to whether a fabrication process was satisfactory or not, which is an unavoidable problem.
Generally, an offset voltage caused by the characteristic variations of the transistors in the portion of the differential circuit is proportional to 1/√{square root over ( )}S when a transistor gate area is set to S. Thus, in order to reduce the offset voltage, the gate area must be set to be considerably large. This causes a chip area to become large and has its own limit when the offset voltage itself is large. Then, in order to solve this problem, a circuit (offset canceling amplifier) for compensating for the output offset that uses a capacitance element is employed.
FIG. 16 shows an example of a typical configuration of the offset canceling amplifier that has been conventionally used. FIG. 17 is a timing chart showing a control method over the offset canceling amplifier in FIG. 16. Referring to FIG. 16, an offset cancel circuit 811 includes an offset detecting capacitor Coff and switches 801 to 803. A voltage Vin at an input terminal VIN of an op-amp 810 is applied to a non-inverting input terminal (+) of the op-amp 810. An output terminal VOUT of the op-amp 810 drives a load (not shown) to be output to an outside and connected to the outside.
Next, an operation of the offset canceling amplifier shown in FIG. 16 will be described using the timing chart in FIG. 17. Referring to FIG. 17, reference numeral S1 corresponds to the switch 801, reference numeral S2 corresponds to the switch 802, and reference numeral S3 corresponds to the switch 803. As shown in FIG. 17, one data output period includes two periods constituted from an offset detection period T01 and an offset compensation output period T02.
During the offset detection period T01, the switches S1 and S2 are set in an ON state, and the switch S3 is set in an OFF state. With this arrangement, one end of the capacitor Coff is connected to the input terminal VIN, and a potential of the capacitor Coff is set to an input potential Vin. Since the switch S1 is in an on stage, a potential at the other end of the capacitor Coff is set to an output voltage Vout. Accordingly, a voltage to be applied to the capacitor Coff becomes as follows:
      Vout    -    Vin    =                    (                  Vin          +          Voff                )            -      Vin        =    Voff  
Electrical charges corresponding to an offset voltage Voff are charged to the capacitor Coff (in the offset detection period).
During the offset compensation output period T02, the switches S1 and S2 are set in an OFF state, and then the switch S3 is set in an ON state. By turning off the switches S1 and S2, the offset voltage Voff is maintained in the capacitor Coff. By turning on the switch S3, an inverting input terminal of the op-amp 810 operates to subtract only a voltage corresponding to the offset voltage Voff from to the output voltage Vout during the period T01. As a result, the output voltage Vout becomes as follows:
  Vout  =                    (                  Vin          +          Voff                )            -      Voff        =    Vin  
Thus, the offset voltages are compensated for, so that a high accuracy voltage can be output (in the offset compensation output period).
However, the conventional offset canceling amplifier described with reference to FIGS. 16 and 17 has the following problem.
That is, the input terminal VIN is connected to the one end of the capacitor Coff in the period T01. Thus, an effective input capacitance of the amplifier increases. The smaller the input capacitance of the amplifier is, the less power consumption is required.
On the other hand, the offset detecting capacitor Coff needs to be of an appropriate and certain size so as to maintain the voltage for a predetermined period and also minimize an offset error caused by electric charges generated at a time of switching off.
Further, in the case of the offset canceling amplifier shown in FIG. 16, the input terminal VIN and the output terminal VOUT are connected through the capacitor Coff in the period T01 to form a positive feedback loop. Accordingly, when a supply capacity of an external power supply for supplying the voltage to the input terminal is small, an output potential may become unstable. For the reason described above, it is not advisable to connect the capacitance element to the input terminal VIN of the amplifier.
Further, in a case of a TFT (thin film transistor) circuit manufactured by a low-temperature polysilicon process, threshold value variations of respective transistors constituting the circuit are extremely large. Thus, in the offset canceling amplifier in FIG. 16, an offset cannot be compensated for completely. Thus, an output deviation may remain, or the circuit may not operate.
As an offset canceling amplifier capable of solving an increase in the input capacitance and a problem on a circuit operation, the amplifier described in Patent Document 1 (JP Patent Kokai Publication No. JP-P2001-292041A) is known. FIG. 18 shows a circuit configuration of the offset canceling amplifier disclosed in Patent Document 1, and FIG. 19 shows a timing chart showing a control method thereof.
An operation of the offset canceling amplifier described in Patent Document 1 will be described below, using the circuit configuration in FIG. 18 and the timing chart in FIG. 19. During the offset detection period T01 of one data output period TDATA, switches S1 and S3 are set in an ON state and a switch S2 is set in an OFF state. In this case, a voltage Vin supplied to an input terminal VIN is supplied to both of a differential pair (constituted from transistors M3 and M4). Thus, the differential pair (constituted from the transistors M3 and M4) operates as a current source for a current mirror circuit (constituted from transistors M1 and M2). In a differential pair (constituted from transistors M5 and M6), the input terminal VIN is connected to a gate of the transistor M6, and an output terminal VOUT is connected to a gate of the transistor M5. At this point, the output terminal voltage Vout is stabilized at a voltage (Vin+Voff) including an offset voltage Voff caused by a characteristic deviation of the transistors within a differential circuit due to a negative feedback operation. In this case, a capacitor C1 is connected to the gate of the transistor M5. Thus, a potential of the voltage Vout in the stabilized state is set in the capacitance.
Next, during the offset compensation output period T02, the switches S1 and S3 are set in an OFF state, and the switch S2 is set in an ON state. In this case, the same voltage as that in the period T01 is kept to be input to the differential pair (constituted from the transistors M5 and M6). Further, the output terminal VOUT is negative feedback connected to a gate of the transistor M3 with a gate of the transistor M4 kept connected to the input terminal. Thus, the output voltage Vout is stabilized at a potential that makes the offset canceling amplifier maintain the same state as that in the period T01. That is, in the period T02, the voltage Vout becomes the voltage Vin, so that the offset is compensated for.
An example of the offset canceling amplifier in Patent Document 1 is excellent in that there is no increase in the input capacitance due to addition of an offset cancel circuit and that operation stability is satisfactory because the capacitance element for offset detection is not connected to the input terminal VIN of the amplifier.
Compared with FIG. 20, the offset canceling amplifier in Patent Document 1 includes the two differential pairs.
On the other hand, as an example of the offset canceling amplifier including one differential pair, there is provided the amplifier described in Patent Document 2. FIG. 20 shows a circuit configuration thereof, and FIG. 21 shows a timing chart showing a control method thereof.
An operation of the offset canceling amplifier described in Patent Document 2 will be described below with reference to the circuit configuration in FIG. 20 and the timing chart in FIG. 21. During an offset detection period T01 of one data output period TDATA, switches S1 and S2 are set in an ON state, while a switch S3 is set in an OFF state. In this case, the same voltage value (Vin: at the input terminal VIN) is supplied to each gate of the differential pair (constituted from transistors M3 and M4). Since each of transistors M1 and M2 is a diode-connected transistor (with a gate thereof and a drain thereof short-circuited), a current that flows through the transistor M3 is converted and output as a gate voltage of the transistor M1, while a current that flows through the transistor M4 is converted and output as a gate voltage of the transistor M2. In this case, a difference between the gate voltages of the transistors M1 and M2 is set in a capacitor Coff.
Ideally, when characteristics of the transistors M1 and M2 in a differential circuit are completely the same and characteristics of the transistors M3 and M4 are completely the same, no offset is generated in an output of the differential circuit, and voltages at both ends of the capacitance element Coff becomes 0V. However, actually, the characteristics of the respective transistors vary due to fabrication variations or the like. The offset is thereby caused, and a voltage corresponding to the offset is set in the capacitance element Coff.
Next, during an offset compensation output period T02, the switches S1 and S2 are set in an OFF state, and the switch S3 is set in an ON state. In this case, the transistors M1 and M2 form a current mirror through the capacitor Coff, the input voltage VIN is connected to the gate of the transistor M4, and the output voltage VOUT is connected to the gate of the transistor M3. Thus, a voltage follower circuit is formed. When a transition from the period T01 to the period T02 is made, the offset voltage of the differential circuits is set to the capacitor Coff. Thus, the gate input voltage of the transistor M1 is different from the gate input voltage of the transistor M2 by a voltage corresponding to the offset voltage. In the period T02, this voltage difference operates to compensate for the offset, so that the voltage VOUT becomes equal to the voltage Vin during the period T02. With regard to quantitative analysis of these offset voltages, a description in paragraphs [0039] to [0043] in Patent Document 2 is referred to.
In the configuration disclosed in Patent Document 2 as well, the capacitance element of an offset detection amount is not connected to the input terminal VIN of the amplifier. Thus, this configuration is excellent in that there is no increase in the input capacitance caused by addition of an offset canceling function.
[Patent Document 1] JP Patent Kokai Publication No. JP-P2001-292041A
[Patent Document 2] JP Patent Kokai Publication No. JP-P2002-202748A
[Non-patent Document 1] “Design of Analog CMOS Integrated Circuits”, Basic Edition, pp. 173-180, translated by Tadahiro Kuroda